NDLI: Effective Power Optimization Under Timing and Voltage-Island Constraints Via Simultaneous <formula formulatype=inline><tex Notation=TeX>$V_{dd}$</tex></formula>, <formula formulatype=inline> <tex Notation=TeX>$V_{th}$</tex></formula> Assignments, Gate Sizing, and Placement

Content Provider	IEEE Xplore Digital Library
Author	Huan Ren Dutt, S.
Copyright Year	1982
Abstract	We present a physical-synthesis based power optimization technique that simultaneously explores the four transforms, multiple Vdd, multiple Vth , cell sizing, and placement, to find a minimum power solution under timing and other constraints. The optimal selection of the design options of all transforms for all cells in the circuit is solved using a new optimization technique called discretized network flow that we have recently developed. Among the constraints we consider, timing and the voltage-island constraints are the two most important and complex ones. The voltage-island constraint specifies the maximum allowed number of voltage islands in the layout, and the requirement that each island be rectangular. We develop an approach that along with the option selection process can simultaneously determine the voltage islands needed, as well as satisfy all given constraints. Experimental results on ISCAS'89 and Faraday benchmarks show that compared to an initial wire length (WL)-optimized placement with high supply and low threshold voltage levels, we obtain a power reduction by up to 42% and an average of 30% for the same delay as that of the initial design. These improvements are also 44-50% relatively better than the improvements yielded by sequentially applying the four power reduction transforms, which is the currently standard method for applying multiple transforms. Finally, compared to an industry tool Synopsys IC Compiler (ICC) that also applies all four transforms, our method reduces power by an additional amount of up to 19%, and an average of 16%.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	746
Ending Page	759
Page Count	14
File Size	1067472
File Format	PDF
ISSN	02780070
Volume Number	30
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transforms Logic gates Optimization Power demand Delay Capacitance voltage-island formation Cell sizing discretized min-cost network flow multiple $V_{dd}$ and $V_{th}$ assignments placement power optimization timing constraint
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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