NDLI: A high performance hardware architecture for multi-frame hierarchical motion estimation

Content Provider	IEEE Xplore Digital Library
Author	Huong Ho Klepko, R. Nam Ninh Demin Wang
Copyright Year	1975
Abstract	This paper presents the architecture design and FPGA implementation of a multi-frame hierarchical motion estimation (MFHME) circuit. The target application of the circuit is high quality motion-compensated video frame rate up-conversion that requires dense motion fields (MF) and accurate motion trajectories. To obtain accurate motion trajectories, the circuit uses two frames as references and calculates the block matching errors for both the luminance and chrominance components of the images. In addition, the sum of squared pixel differences, instead of the sum of the absolute pixel differences, is used as the metric of the block matching errors in order to further improve the accuracy of the estimated motion trajectories. To achieve low computation complexity, the circuit has been designed based on a hierarchical structure and a pre-computed lookup table is used to provide the squared pixel differences. The implementation result shows that the circuit is able to support the frame rate up-conversion of high definition video (1080P format) from 30 to 60 frames per second at a clock frequency of 55 MHz.
Sponsorship	IEEE Consumer Electronics Society
File Size	325318
File Format	PDF
ISSN	00983063
Volume Number	57
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Pixel Computer architecture Random access memory Motion estimation Trajectory Hardware Field programmable gate arrays frame rate up-conversion FPGA implementation hardware architecture
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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