NDLI: Degradation of Amorphous Silicon Thin Film Transistors Under Negative Gate Bias Stress

Content Provider	IEEE Xplore Digital Library
Author	Dapeng Zhou Mingxiang Wang Shengdong Zhang
Copyright Year	1963
Abstract	Degradation of amorphous silicon thin-film transistors under negative gate bias stresses is systematically investigated. It is found that both state creation and hole trapping contribute to device threshold voltage V_th shifts. For direct-current stresses, state creation dominates in low-stress amplitude conditions, whereas hole trapping could dominate the second-stage degradation in high-stress amplitude conditions. For alternating-current stresses, it is found that domination of state creation or hole trapping mechanisms depends on stress frequency f, temperature, amplitude, and stress time. As a result, different turnaround phenomena of V_th degradation are observed. Both state creation and hole trapping mechanisms are enhanced by higher stress temperatures and amplitudes. Based on an RC delay model, both f- and duty-ratio-dependent degradation under low-f stress conditions can be understood, whereas a recovery phenomenon under high- f stress conditions can be explained by the hole trapping/emission mechanism. Device leakage current I_off decreases under low-f stress but increases under high- f stress. State creation is considered responsible for the I_off reduction, whereas hole injection is considered responsible for the I_off increase.
Sponsorship	IEEE Electron Devices Society
Starting Page	3422
Ending Page	3427
Page Count	6
File Size	823630
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress Degradation Charge carrier processes Logic gates Delay effects Delay Insulators thin-film transistors (TFTs) Amorphous silicon (a-Si) gate bias stress
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A Two-Stage Degradation Model of p-Channel Low-Temperature Poly-Si Thin-Film Transistors Under Positive Bias Temperature Stress

Amorphous InGaZnO Thin-Film Transistors—Part II: Modeling and Simulation of Negative Bias Illumination Stress-Induced Instability

Two-Stage Degradation of p-Channel Poly-Si Thin-Film Transistors Under Dynamic Negative Bias Temperature Stress

Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Investigating the Drain-Bias-Induced Degradation Behavior Under Light Illumination for InGaZnO Thin-Film Transistors

Analysis of Degradation Mechanisms in Low-Temperature Polycrystalline Silicon Thin-Film Transistors under Dynamic Drain Stress

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Degradation of Amorphous Silicon Thin Film Transistors Under Negative Gate Bias Stress

Similar Documents

A Two-Stage Degradation Model of p-Channel Low-Temperature Poly-Si Thin-Film Transistors Under Positive Bias Temperature Stress

Amorphous InGaZnO Thin-Film Transistors—Part II: Modeling and Simulation of Negative Bias Illumination Stress-Induced Instability

Two-Stage Degradation of p-Channel Poly-Si Thin-Film Transistors Under Dynamic Negative Bias Temperature Stress

Light Effect on Negative Bias-Induced Instability of HfInZnO Amorphous Oxide Thin-Film Transistor

Negative Bias Temperature Instability Dominated Degradation of Metal-Induced Laterally Crystallized p-Type Polycrystalline Silicon Thin-Film Transistors

Two-step Electrical Degradation Behavior in α-InGaZnO Thin-film Transistor Under Gate-bias Stress

Investigating the Drain-Bias-Induced Degradation Behavior Under Light Illumination for InGaZnO Thin-Film Transistors

Analysis of Degradation Mechanisms in Low-Temperature Polycrystalline Silicon Thin-Film Transistors under Dynamic Drain Stress

Characterization of DC-Stress-Induced Degradation in Bridged-Grain Polycrystalline Silicon Thin-Film Transistors

Degradation of Amorphous Silicon Thin Film Transistors Under Negative Gate Bias Stress