NDLI: A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges

Content Provider	IEEE Xplore Digital Library
Author	Te-Kuang Chiang
Copyright Year	1963
Abstract	Based on the perimeter-weighted-sum method and scaling theory, a compact threshold voltage model for surrounding-gate MOSFETs with localized interface trapped charges is developed by considering the effects of equivalent oxide charges on the flat-band voltage. The model shows how various charge conditions such as the positive/negative trapped charges and device structure parameters such as the silicon thickness, oxide thickness, and channel length affect the threshold voltage behavior. The model is verified by the 3-D device simulator and can be efficiently used to explore hot-carrier-induced threshold voltage degradation of the charge-trapped memory device.
Sponsorship	IEEE Electron Devices Society
Starting Page	567
Ending Page	571
Page Count	5
File Size	510499
File Format	PDF
ISSN	00189383
Volume Number	58
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Threshold voltage MOSFETs Silicon Degradation Logic gates Solid modeling surrounding-gate MOSFETs Hot-carrier-induced threshold voltage
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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A Compact Model for Threshold Voltage of Surrounding-Gate MOSFETs With Localized Interface Trapped Charges