NDLI: Modeling Heat Transport in Thermal Interface Materials Enhanced With MEMS-Based Microinterconnects

Content Provider	IEEE Xplore Digital Library
Author	Fan Zhou Arunasalam, P. Murray, B.T. Sammakia, B.
Copyright Year	1999
Abstract	Thermal management of device-level packaging continues to present many technical challenges in the electronics industry. In a device/heat sink assembly, the highest resistance to heat flow typically comes from the thermal interface material (TIM). The thermal conductivities of TIMs remain in the range of 1-4 W/mK due to the properties and structure of small dispersed solids in polymer matrices. As a result of the rising design power and heat flux at the silicon die, new ways to improve the effective in situ thermal conductivity of interface materials are required. This paper analyzes a unique TIM enhanced with ultrahigh-density wafer-level thin film-compliant interconnects referred to as smart three axis compliant (STAC) interconnects. MEMS technology is used to directly fabricate STAC interconnects onto a silicon wafer and embed them into the TIM to provide an enhanced conductive path between the die/package and the heat sink. Here, results from a theoretical analysis of the thermal conduction in a TIM embedded with STAC interconnects are reported. The objective of the study is to provide comprehensive design strategies for effective implementation of this type of TIM for specific applications. Parametric studies are performed to examine the thermal resistance of the microinterconnect-enhanced TIM for varying materials, configurations, and geometry of the microinterconnects. A periodic element model of a chip-TIM configuration with top heat sink is used to evaluate the conductive effect of the microinterconnects. In addition, an investigation of the conductive transport in a more complicated chip stack is considered. A 3-D thermal analysis is conducted for a multichip stack package with and without through-silicon vias. The numerical results show that the microinterconnects significantly improve the thermal performance of the TIM. Finally, further steps toward achieving a chip-level design optimization and fabrication process using a STAC microinterconnect structured TIM is proposed.
Sponsorship	IEEE Components, Packaging, and Manufacturing Technology Society
Starting Page	16
Ending Page	24
Page Count	9
File Size	872523
File Format	PDF
ISSN	15213331
Volume Number	33
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-03-01
Publisher Place	U.S.A.
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electronic packaging thermal management Thermal conductivity Conducting materials Heat sinks Thermal resistance Thermal management Resistance heating Silicon Thermal management of electronics Electronics industry thermal interface material MEMS numerical modeling STAC interconnect thermal management
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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