NDLI: A Multitransform Architecture for H.264/AVC High-Profile Coders

Content Provider	IEEE Xplore Digital Library
Author	Woong Hwangbo Chong-Min Kyung
Copyright Year	1999
Abstract	This paper presents a high-throughput, cost-effective implementation of six different integer transforms in the H.264/AVC high-profile coders, i.e., 4 × 4 forward, 4 × 4 inverse, forward Hadamard, inverse Hadamard, 8 × 8 forward, and 8 × 8 inverse transform, all integrated as a shared hardware. The 4 × 4 transform matrices are regularized by using permutation, partitioned into 2 × 2 blocks, and factored for maximal hardware sharing. By using two types of 4 × 4 transform matrices included in an 8 × 8 transform matrix, two different 8 × 8 transforms are both described as three steps and unified with minor modification. To improve throughput of the transform, two independent 4 × 4 transform blocks within the 8 × 8 transform block operate in parallel in the 4 × 4 transform mode, while the two-stage pipelined architecture is used in the 8 × 8 transform mode. Using 0.18-¿m CMOS technology, the maximum operating frequency of the proposed multitransform architecture is 200 MHz, which achieves 4.1 Gpixels/sec throughput rate with the hardware cost of 63618 gates. Compared with existing designs, the proposed design delivers at least 54% higher throughput at 38% higher throughput/area ratio in Adaptive Block-size Transform (ABT) mode.
Sponsorship	IEEE Signal Processing Society IEEE Circuits and Systems Society IEEE Communications Society IEEE Computer Society
Starting Page	157
Ending Page	167
Page Count	11
File Size	1418451
File Format	PDF
ISSN	15209210
Volume Number	12
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic voltage control Throughput Hardware Video compression Error correction Error correction codes CMOS technology Arithmetic Testing Frequency VLSI design DCT H.264/AVC Hadamard transform IDCT integer transform
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering Computer Science Applications Media Technology

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A high normalized aggregate throughput SoC-based inverse integer transform design for H.264/AVC

Adaptive Truncation Algorithm for Hadamard-Transformed H.264/AVC Lossless Video Coding

- h.264/avc - - - - - - - - - - - - - - - - - - ─ - dct - idct.

High throughput 2-D transform architectures for H.264 advanced video coders

Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard

Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard

Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard

Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt

A Multitransform Architecture for H.264/AVC High-Profile Coders

Similar Documents

A high normalized aggregate throughput SoC-based inverse integer transform design for H.264/AVC

Adaptive Truncation Algorithm for Hadamard-Transformed H.264/AVC Lossless Video Coding

- h.264/avc - - - - - - - - - - - - - - - - - - ─ - dct - idct.

High throughput 2-D transform architectures for H.264 advanced video coders

Register Length Analysis and VLSI Optimization of VBS Hadamard Transform in H.264/AVC

High throughput multitransform and multiparallelism IP for H.264/AVC video compression standard

Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard

Forward and inverse 2-D DCT architectures targeting HDTV for H.264/AVC video compression standard

Hardware optimizations of variable block size Hadamard transform for H.264/AVC FRExt

A Multitransform Architecture for H.264/AVC High-Profile Coders