NDLI: An improved low-power high-throughput log-MAP turbo decoder

Content Provider	IEEE Xplore Digital Library
Author	Karim, S.M. Chakrabarti, I.
Copyright Year	1975
Abstract	This paper presents an efficient implementation of a high-throughput low-power turbo decoder. The design of the component decoder has been optimized so as to achieve low power implementation of the turbo decoder. A collision-free interleaver has been designed for appropriate parallel decoding operations. Performance enhancing techniques such as parallel processing and pipelining have been applied to realize the highly recursive and complex maximum a posteriori probability (MAP) decoder. Area, power and throughput of the proposed decoder architecture compare favorably with those of an architecture which has been recently reported in literature. The designed decoder, which achieves a throughput of 930 Mbps while consuming 265 mW of power, can be considered to be suitable for a number of real time applications.
Sponsorship	IEEE Consumer Electronics Society
File Size	592924
File Format	PDF
ISSN	00983063
Volume Number	56
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Iterative decoding Throughput Delay Turbo codes Parallel processing Pipeline processing Parallel architectures Bit error rate Design optimization Error correction Turbo codes, parallel architecture, collision free interleaver, border metric storage
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Media Technology

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