NDLI: A Low-Voltage Micropower Asynchronous Multiplier With Shift

Content Provider	IEEE Xplore Digital Library
Author	Bah-Hwee Gwee Chang, J.S. Yiqiong Shi Chien-Chung Chua Kwen-Siong Chong
Copyright Year	2004
Abstract	The design of a low-voltage micropower asynchronous (async) signed truncated multiplier based on a shift-add structure for power-critical applications such as the low-clock-rate (<4 MHz) hearing aids is described. The emphases of the design are micropower operation and small IC area, and these attributes are achieved in several ways. First, a maximum of three signed power-of-two terms accompanied with sign magnitude data representation is used for the multiplier operand. Second, the least significant partial products are truncated to yield a 16-bit signed product. An error correction methodology is proposed to mitigate, where appropriate, the arising truncation errors. The errors arising from truncation and the effectiveness of the error correction are analytically derived. Third, a low-power shifter design and an internal latch adder are adopted. Finally, a power-efficient speculative delay line is proposed to time the async operation of the various circuit modules. A comparison with competing synchronous and async designs shows that the proposed design features the lowest power dissipation (5.86 muW at 1.1 V and 1 MHz) and a very competitive IC area (0.08 mm² using a 0.35-mum CMOS process). The application of the proposed multiplier for realizing a digital filter for a hearing aid is given.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1349
Ending Page	1359
Page Count	11
File Size	1414532
File Format	PDF
ISSN	15498328
Volume Number	56
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Error correction Hearing aids Finite wordlength effects Error analysis Latches Adders Delay lines Power dissipation CMOS integrated circuits CMOS process shift–add multiplier Asynchronous (async) circuits finite-impulse response (FIR) filter low power
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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