NDLI: A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects

Content Provider	IEEE Xplore Digital Library
Author	Ahmed, N. Tehranipoor, M.
Copyright Year	1982
Abstract	Interconnect defects such as weak resistive opens, shorts, and bridges increase the path delay affected by a pattern during manufacturing test but are not significant enough to cause a failure at functional frequency. In this paper, a new faster-than-at-speed method is presented for delay test pattern application to screen small delay defects. Given a test pattern set, the technique groups the patterns into multiple subsets with close path delay distribution and determines an optimal test frequency considering both positive slack and performance degradation due to IR-drop effects. Since, the technique does not increase the test frequency to an extent that any paths exercised at the rated functional frequency may fail, it avoids any scan flip-flop masking. As most semiconductor companies currently deploy compression technologies to reduce test costs, scan-cell masking is highly undesirable for pattern modification as it would imply pattern count increase and might result in pattern regeneration. Therefore, our solution is more practical as the test engineer can run the same pattern set without any changes to the test flow other than the at-speed test frequency.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1573
Ending Page	1582
Page Count	10
File Size	1706668
File Format	PDF
ISSN	02780070
Volume Number	28
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Frequency Delay effects Circuit faults Timing Manufacturing Flip-flops Costs Bridge circuits Degradation test generation Delay test supply noise
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Active timing multilevel fault-simulation with switch-level accuracy

Longest-path selection for delay test under process variation

On Complete Functional Broadside Tests for Transition Faults

ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Path-delay-fault testable nonscan sequential circuits

SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation

A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects

Similar Documents

Active timing multilevel fault-simulation with switch-level accuracy

Longest-path selection for delay test under process variation

On Complete Functional Broadside Tests for Transition Faults

ATPG-XP: Test Generation for Maximal Crosstalk-Induced Faults

Improved Launch for Higher TDF Coverage With Fewer Test Patterns

Pattern generation for delay testing and dynamic timing analysis considering power-supply noise effects

Path-delay-fault testable nonscan sequential circuits

SPADES-ACE: A simulator for path delay faults in sequential circuits with extensions to arbitrary clocking schemes

Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation

A Novel Faster-Than-at-Speed Transition-Delay Test Method Considering IR-Drop Effects