NDLI: Real-Time Lossless Compression for Silicon Debug

Content Provider	IEEE Xplore Digital Library
Author	Daoud, E.A. Nicolici, N.
Copyright Year	1982
Abstract	Silicon debug is becoming a key step in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre-silicon verification. To address the lack of observability for the internal circuit nodes during silicon debug, embedded logic analysis enables real-time data acquisition from a limited number of internal signals. In this paper, we propose a novel architecture for embedded logic analysis that enables real-time lossless compression of debug data. To quantify the gain from using lossless compression in embedded logic analysis, we present a new compression-ratio metric that captures the trade-off between the area and the increase in the observation window. The proposed architecture is particularly suitable for in-field debugging on application boards, which have asynchronous events that inhibit the deterministic replay of debug experiments.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1387
Ending Page	1400
Page Count	14
File Size	1010211
File Format	PDF
ISSN	02780070
Volume Number	28
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon Computer bugs Logic circuits Manufacturing Time to market Fabrication Circuit testing Logic testing Software debugging Failure analysis silicon debug Embedded logic analysis lossless compression
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation

On-chip support for software verification and debug in multi-core embedded systems

A Formal Approach for Debugging Arithmetic Circuits

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

Automating Postsilicon Debugging and Repair

Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics

Real-Time Lossless Compression for Silicon Debug

Similar Documents

Design-for-Debug Architecture for Distributed Embedded Logic Analysis

Post-Silicon Bug Localization in Processors Using Instruction Footprint Recording and Analysis (IFRA)

Algorithms for State Restoration and Trace-Signal Selection for Data Acquisition in Silicon Debug

Embedded Debug Architecture for Bypassing Blocking Bugs During Post-Silicon Validation

On-chip support for software verification and debug in multi-core embedded systems

A Formal Approach for Debugging Arithmetic Circuits

Effective Post-Silicon Validation of System-on-Chips Using Quick Error Detection

Automating Postsilicon Debugging and Repair

Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics

Real-Time Lossless Compression for Silicon Debug