NDLI: System-Level Bus-Based Communication Architecture Exploration Using a Pseudoparallel Algorithm

Content Provider	IEEE Xplore Digital Library
Author	Lih-Yih Chiou Yi-Siou Chen Chih-Hsien Lee
Copyright Year	1982
Abstract	Growing complexity in system-on-a-chip (SoC) design demands effective approaches to explore various architectures quickly for the target applications. With the common use of intellectual properties (IPs) in SoC and the large amount of data interchanges among IPs, communication architecture significantly affects the system in terms of power and performance. Therefore, designers should carefully plan the communication architecture to meet the power and performance requirements. While repeatedly performing a power optimization under a performance constraint approach N times seems practical for the power and performance co-exploration, the time required to explore such solutions inevitably increases, since there are numerous performance constraints. This paper presents a pseudo-parallel method for bus architecture exploration at the system level (PBAES) to speedup the power and performance of co-exploration time. PBAES can intelligently search interesting portions of the design space to enhance the efficiency of co-exploration, and share the candidate solutions of each to achieve a more rapid overall exploration. The experimental results indicate that PBAES is 1.6 times to 14 times faster than an approach without the pseudo-parallel method with a generated architecture of similar quality.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	1213
Ending Page	1223
Page Count	11
File Size	670438
File Format	PDF
ISSN	02780070
Volume Number	28
Issue Number	8
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-08-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Space exploration System-on-a-chip Computer architecture Power system modeling Algorithm design and analysis Intellectual property Constraint optimization Time factors System performance system-on-a-chip (SoC) Design space exploration on-chip communication architecture power-performance tradeoffs
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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