NDLI: Large-Scale SRAM Variability Characterization in 45 nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Zheng Guo Carlson, A. Liang-Teck Pang Duong, K.T. Tsu-Jae King Liu Nikolic, B.
Copyright Year	1966
Abstract	Increased process variability presents a major challenge for future SRAM scaling. Fast and accurate validation of SRAM read stability and writeability margins is crucial for estimating yield in large SRAM arrays. Conventional SRAM read/write metrics are characterized through test structures that are able to provide limited hardware measurement data and cannot be used to investigate cell bit fails in functional SRAM arrays. This work presents a method for large-scale characterization of read stability and writeability in functional SRAM arrays using direct bit-line measurements. A test chip is implemented in a 45 nm CMOS process. Large-scale SRAM read/write metrics are measured and compared against conventional SRAM stability metrics. Results show excellent correlation to conventional SRAM read/write metrics as well as V_MIN measurements near failure.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	3174
Ending Page	3192
Page Count	19
File Size	5366948
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Large-scale systems Random access memory Semiconductor device measurement Stability CMOS process Cache memory Testing Failure analysis Hardware Switches variability CMOS measurement noise margins SRAM
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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