NDLI: A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers

Content Provider	IEEE Xplore Digital Library
Author	Eliezer, O.E. Staszewski, R.B. Bashir, I. Bhatara, S. Balsara, P.T.
Copyright Year	1966
Abstract	A novel approach for mitigation of self-interference in highly-integrated wireless transceivers is presented. Several examples of possible applications of this approach in a wireless cellular transceiver system-on-chip (SoC) are listed, and the application of one example is presented in detail. Mathematical analysis, simulation results, measurements, and implementation details are provided for the demonstrated technique, which was designed to minimize jitter induced onto the reference clock of a GSM transceiver's PLL. Excessive jitter on this clock, caused by multiple RF aggressors centered at harmonics of it, creates amplified in-band phase-noise at the RF output of the PLL, resulting in failures in the transmitter's performance. The identification of this highly complex interference mechanism, which represents a significant part of this work, is discussed in detail, as is the implemented solution. The presented phase-adjustment technique, leveraging specific features of the digitally intensive PLL and available digital-signal-processing resources, is demonstrated in a GSM system-on-chip (SoC) based on the Digital RF Processor (DRPtrade) technology in 90 nm CMOS. As it does not involve dedicated hardware, nor does it noticeably increase the current consumption, it represents a cost-free solution in the final product.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1436
Ending Page	1453
Page Count	18
File Size	2109153
File Format	PDF
ISSN	00189200
Volume Number	44
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transceivers Phase locked loops Radio frequency System-on-a-chip Jitter Clocks GSM Mathematical analysis Analytical models Radiofrequency identification system-on-chip (SoC) All-digital PLL (ADPLL) Digital RF Processor (DRP) interference mitigation jitter phase trajectory error (PTE) self-interference
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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