NDLI: Low-Cost CP-PLL DFT Structure Implementation for Digital Testing Application

Content Provider	IEEE Xplore Digital Library
Author	Chun-Lung Hsu Yi-Ting Lai
Copyright Year	1963
Abstract	This paper proposes a low-cost design-for-testability (DFT) structure for a classical charge-pump phase-locked loop (CP-PLL) circuit to allow simple digital testing. The proposed CP-PLL DFT structure uses the existing charge-pump circuit and voltage-controlled oscillator (VCO) as a stimulus generator and a measuring device, respectively. Thus, no extra test stimulus or measured instruments are required during testing. The primary advantage is that the analog blocks of the CP-PLL are unchanged and that the test output is purely digital, ensuring that the characteristics of CP-PLL are unaltered and that a suitable on-chip design can be developed using the proposed CP-PLL DFT structure. Fault simulation results indicate that the proposed CP-PLL DFT structure possesses high fault coverage (97.9%). In addition, the physical chip design is presented to show low area overhead (4.48%) and little degradation in performance.
Sponsorship	IEEE Instrumentation and Measurement Society Bureau international des poids et mesures IEEE International Bureau of Weights and Measures (BIPM) URSI NBS Agency Ind. Sci. & Technol., Min. Int. Trade & Ind. Sci. Council Japan International Union of Pure and Applied Physics (IUPAP) NIST NRCC National Conference of Standards Laboratories (NCSL) Allen Osborne Associates Andeen-Hagerling, Inc. Ballantine Lab. Inc. Clarke-Hess Communications Research Corp. Fluke Corporation Guildline Instruments Hewlett-Packard Co. Julie Res. Lab. Inc. Keithley Instruments, Inc. Measurements International Ltd. Canada QuadTech Inc. Quantum Design Inc. Rotek Instrum. Corp. Tegam Inc. Tektronix Inc
Starting Page	1897
Ending Page	1906
Page Count	10
File Size	1113460
File Format	PDF
ISSN	00189456
Volume Number	58
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing Design for testability Charge pumps Voltage-controlled oscillators Circuit faults Phase locked loops Current measurement Instruments Chip scale packaging Degradation fault coverage Area overhead charge-pump phase-locked loop (CP-PLL) design for testability (DFT) digital testing
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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