NDLI: Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

Content Provider	IEEE Xplore Digital Library
Author	Sharma, R.K. Gupta, R. Gupta, M. Gupta, R.S.
Copyright Year	1963
Abstract	The dual-material double-gate (DMDG) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) is the leading contender for sub-100-nm devices because it utilizes the benefits of both double-gate and dual-material-gate structures. One major issue of concern in the DMDG-MOSFET is the alignment between the top and the bottom gate that critically influences the device performance. In this paper, we have investigated the effects of gate misalignment in the DMDG SOI n-MOSFET. In this regard, analytical modeling and extensive simulations have been carried out to analyze the gate misalignment effects on device performance like surface potential, electric field, threshold voltage, subthreshold slope, drain-induced barrier lowering, drain current, and transconductance. Considering the fact that gate misalignment can occur on any side of the gate, both source- and drain-side misalignments have been discussed. Analytical and simulated results are found to be in good agreement, which authenticate our proposed model for the DMDG structure.
Sponsorship	IEEE Electron Devices Society
Starting Page	1284
Ending Page	1291
Page Count	8
File Size	420119
File Format	PDF
ISSN	00189383
Volume Number	56
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates Threshold voltage Electric potential MOSFET circuits Analytical models Metals Silicon 3-D ATLAS device simulation Drain current dual-material double gate (DMDG) gate misalignment subthreshold slope threshold voltage transconductance
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Quantum Analytical Modeling for Device Parameters and $I$ – $V$ Characteristics of Nanoscale Dual-Material Double-Gate Silicon-on-Nothing MOSFET

TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET

Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

Simple and Efficient MASTAR Threshold Voltage and Subthreshold Slope Models for Low-Doped Double-Gate MOSFET

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

Precise Analytical Model for Short-Channel Quadruple-Gate Gate-All-Around MOSFET

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis

Similar Documents

Quantum Analytical Modeling for Device Parameters and $I$ – $V$ Characteristics of Nanoscale Dual-Material Double-Gate Silicon-on-Nothing MOSFET

TCAD Assessment of Device Design Technologies for Enhanced Performance of Nanoscale DG MOSFET

A new dual-material double-gate (DMDG) nanoscale SOI MOSFET-two-dimensional analytical modeling and simulation

Quantum Analytical Model for Inversion Charge and Threshold Voltage of Short-Channel Dual-Material Double-Gate SON MOSFET

Spatial Composition Grading of Binary Metal Alloy Gate Electrode for Short-Channel SOI/SON MOSFET Application

Simple and Efficient MASTAR Threshold Voltage and Subthreshold Slope Models for Low-Doped Double-Gate MOSFET

Compact Modeling of a Generic Double-Gate MOSFET With Gate–S/D Underlap for Subthreshold Operation

Precise Analytical Model for Short-Channel Quadruple-Gate Gate-All-Around MOSFET

Device Design Engineering for Optimum Analog/RF Performance of Nanoscale DG MOSFETs

Dual-Material Double-Gate SOI n-MOSFET: Gate Misalignment Analysis