NDLI: High-Performance Low-Power Selective Precharge Schemes for Address Decoders

Content Provider	IEEE Xplore Digital Library
Author	Turi, M.A. Delgado-Frias, J.G.
Copyright Year	2004
Abstract	Two novel address decoder schemes using selective precharging are presented and analyzed in this paper. These schemes, the AND-NOR and sense amplifier (sense-amp) decoders, are compared to the NOR decoder using 90-nm CMOS technology. The sense-amp decoder dissipates between 29.5% and 50.1% and the AND-NOR decoder dissipates between 73.7% and 104.4% of the energy dissipated by the NOR decoder. The delay of the Sense-Amp decoder is 69.2% and the delay of the AND-NOR decoder is 80.8% of the nor decoder delay.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	917
Ending Page	921
Page Count	5
File Size	774241
File Format	PDF
ISSN	15497747
Volume Number	55
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Decoding CMOS technology Delay Computational modeling Circuit simulation Clocks Power generation Random access memory Performance analysis Synchronization sense amplifier (Sense-Amp) Address decoder high performance selective precharge
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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High-Performance Low-Power Selective Precharge Schemes for Address Decoders