NDLI: A low-cost serial decoder architecture for low-density parity-check convolutional codes

Content Provider	IEEE Xplore Digital Library
Author	Bates, S. Zhengang Chen Gunthorpe, L. Pusane, A.E. Zigangirov, K.Sh. Costello Jr., D.J.
Copyright Year	2004
Abstract	We propose a low-cost serial decoder architecture for low-density parity-check convolutional codes (LDPC-CCs). It has been shown that LDPC-CCs can achieve comparable performance to LDPC block codes with constraint length much less than the block length. The proposed serial decoder architecture for LDPC-CCs uses a single decoding processor. Terminated data frames are sent through the processor iteratively until correctly decoded or a maximum number of iterations is reached. This architecture saves memory consumption and uses a very small number of logic elements, making it especially suitable for strong LDPC-CCs with large code memory. The proposed architecture is realized for a (2048,3,6) regular LDPC-CC on an Altera Stratix FPGA. With a maximum of 100 iterations, the design achieves up to 9-Mb/s throughput using only a very small portion of the field-programmable gate array resources.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1967
Ending Page	1976
Page Count	10
File Size	884857
File Format	PDF
ISSN	15498328
Volume Number	55
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parity check codes Convolutional codes Iterative decoding Field programmable gate arrays Throughput Circuits Parallel architectures Block codes Memory architecture Belief propagation high-speed integrated circuits Convolutional codes (CCs) data communication error correction codes High-speed integrated circuits Data communication Error correction codes
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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