NDLI: Low-Power Programmable Pseudorandom Word Generator and Clock Multiplier Unit for High-Speed SerDes Applications

Content Provider	IEEE Xplore Digital Library
Author	Wei-Zen Chen Guan-Sheng Huang
Copyright Year	2004
Abstract	This paper presents the design of a low-power programmable pseudorandom word generator (PRWG) and a low-noise clock multiplier unit (CMU) for high-speed SerDes applications. The PRWG is capable of producing test patterns with sequence length of 2⁷ -1, 2¹⁰ -1, 2¹⁵ -1, 2 ²³ -1, and 2³¹ -1 b according to CCITT recommendations, and the random word is 16-bit wide. High-speed and low-power operations of the PRWG are achieved by parallel feedback techniques. The measured jitter of the CMU is only 3.56 ps_rms, and the data jitter at the PRWG output is mainly determined by the CMU. Implemented in an 0.18-mum CMOS process, the power dissipation for the PRWG is only 10.8 mW, and the CMU consumes about 87 mW from a 1.8-V supply. This PRWG can be used as a low-cost substitute for external parallel test pattern generators.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1495
Ending Page	1501
Page Count	7
File Size	1526510
File Format	PDF
ISSN	15498328
Volume Number	55
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Jitter Bit error rate Built-in self-test Test pattern generators Automatic testing Transceivers Circuit testing Feedback Signal analysis SerDes Clock multiplier unit (CMU) parallel feedback shift register (PFSR) psuedorandom word generator (PRWG) parallel feedback shift register Clock multiplier unit PRWG
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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