NDLI: Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length

Content Provider	IEEE Xplore Digital Library
Author	Chun Jason Xue Zhiping Jia Zili Shao Meng Wang Sha, E.H.-M.
Copyright Year	2004
Abstract	Reducing address arithmetic operations by optimization of address offset assignment greatly improves the performance of digital signal processor (DSP) applications. However, minimizing address operations alone may not directly reduce code size and schedule length for DSPs with multiple functional units. Little research work has been conducted on loop optimization with address offset assignment problem for architectures with multiple functional units. In this paper, we combine loop scheduling, array interleaving, and address assignment to minimize the schedule length and the number of address operations for loops on DSP architectures with multiple functional units. Array interleaving is applied to optimize address assignment for arrays in loop scheduling process. An algorithm, address operation reduction rotation scheduling (AORRS), is proposed. The algorithm minimizes both schedule length and the number of address operations. with to list scheduling, AORRS shows an average reduction of 38.4% in schedule length and an average reduction of 31.7% in the number of address operations. Compared with rotation scheduling, AORRS shows an average reduction of 15.9% in schedule length and 33.6% in the number of address operations.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	379
Ending Page	389
Page Count	11
File Size	796907
File Format	PDF
ISSN	15498328
Volume Number	55
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Processor scheduling Digital signal processing Interleaved codes Registers Computer science Digital arithmetic Digital signal processors Signal processing algorithms Scheduling algorithm Microcontrollers digital signal processor (DSP) Array not given
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units

Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment

Complex Floating Point—A Novel Data Word Representation for DSP Processors

Efficient assignment and scheduling for heterogeneous DSP systems

Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing

Multiprocessor DSP with multistage switching network for video coding

Efficient processor assignment algorithms and loop transformations for executing nested parallel loops on multiprocessors

Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs

A floating-point FPGA-based self-tuning regulator

Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length

Similar Documents

Optimizing Address Assignment and Scheduling for DSPs With Multiple Functional Units

Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment

Complex Floating Point—A Novel Data Word Representation for DSP Processors

Efficient assignment and scheduling for heterogeneous DSP systems

Hardware Implementation of EMD Using DSP and FPGA for Online Signal Processing

Multiprocessor DSP with multistage switching network for video coding

Efficient processor assignment algorithms and loop transformations for executing nested parallel loops on multiprocessors

Optimal Mapping of DSP Algorithms on Commercially Available Off-The-Shelf (COTS) VLIW DSPs

A floating-point FPGA-based self-tuning regulator

Optimized Address Assignment With Array and Loop Transformations for Minimizing Schedule Length