NDLI: FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic

Content Provider	IEEE Xplore Digital Library
Author	Meher, P.K. Chandrasekaran, S. Amira, A.
Copyright Year	1991
Abstract	In this paper, we present the design optimization of one- and two-dimensional fully pipelined computing structures for area-delay-power-efficient implementation of finite-impulse-response (FIR) filter by systolic decomposition of distributed arithmetic (DA)-based inner-product computation. The systolic decomposition scheme is found to offer a flexible choice of the address length of the lookup tables (LUT) for DA-based computation to decide on suitable area time tradeoff. It is observed that by using smaller address lengths for DA-based computing units, it is possible to reduce the memory size, but on the other hand that leads to increase of adder complexity and the latency. For efficient DA-based realization of FIR filters of different orders, the flexible linear systolic design is implemented on a Xilinx Virtex-E XCV2000E FPGA using a hybrid combination of Handel-C and parameterizable VHDL cores. Various key performance metrics such as number of slices, maximum usable frequency, dynamic power consumption, energy density, and energy throughput are estimated for different filter orders and address lengths. Analysis of the results obtained indicate that performance metrics of the proposed implementation is broadly in line with theoretical expectations. It is found that the choice of address length yields the best of area-delay-power-efficient realizations of the FIR filter for various filter orders. Moreover, the proposed FPGA implementation is found to involve significantly less area-delay complexity compared with the existing DA-based implementations of FIR filter.
Sponsorship	IEEE Signal Processing Society
Starting Page	3009
Ending Page	3017
Page Count	9
File Size	826618
File Format	PDF
ISSN	1053587X
Volume Number	56
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Finite impulse response filter Arithmetic Distributed computing Table lookup Measurement Frequency estimation Design optimization Delay Energy consumption systolic array Distributed arithmetic field-programmable gate arrays (FPGA) finite-impulse-response (FIR) filter linear convolution
Content Type	Text
Resource Type	Article
Subject	Signal Processing Electrical and Electronic Engineering

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