NDLI: Parallel ADI-BOR-FDTD Algorithm

Content Provider	IEEE Xplore Digital Library
Author	Stefanski, T. Drysdale, T.D.
Copyright Year	2001
Abstract	We present a parallel implementation of the alternating direction implicit-body of revolution-finite difference time domain (ADI-BOR-FDTD) method on a high performance computer using a Message Passing Interface (MPI) library. In BOR-FDTD codes, the body of revolution symmetry is exploited to reduce the computational complexity by projecting the 3-D Yee-cell in cylindrical coordinates onto a 2-D plane. Adopting an implicit update scheme (ADI) frees the time-step size from the Courant-Friedrichs-Lewy time step constraint. We demonstrate further performance gains by parallelizing the algorithm, although the communication overhead between processors is proportional to the area of the domain. In our parallel ADI-BOR-FDTD method each tridiagonal matrix system is solved by a single processor, with the parallel computer architecture being exploited to solve multiple systems at the same time. We benchmarked our code on an IBM p690 symmetric multiprocessor revealing excellent scalability and efficiency.
Sponsorship	IEEE Microwave Theory and Techniques Society
Starting Page	722
Ending Page	724
Page Count	3
File Size	230184
File Format	PDF
ISSN	15311309
Volume Number	18
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer interfaces Concurrent computing High performance computing Message passing Libraries Computational complexity Time factors Performance gain Symmetric matrices Computer architecture parallel processing Alternating direction implicit finite-difference time-domain (ADI-FDTD) bodies of revolution (BOR)
Content Type	Text
Resource Type	Article
Subject	Condensed Matter Physics Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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