NDLI: Stress-Induced Hump Effects of p-Channel Polycrystalline Silicon Thin-Film Transistors

Content Provider	IEEE Xplore Digital Library
Author	Ching-Fang Huang Cheng-Yi Peng Ying-Jhe Yang Hung-Chang Sun Hung-Chih Chang Ping-Sheng Kuo Huan-Lin Chang Chee-Zxaing Liu Chee Wee Liu
Copyright Year	1980
Abstract	Positive bias temperature instability in p-channel polycrystalline silicon thin-film transistors is investigated. The stress-induced hump in the subthreshold region is observed and is attributed to the edge transistor along the channel width direction. The electric field at the corner is higher than that at the channel due to thinner gate insulator and larger electric flux density at the corner. The current of edge transistor is independent of the channel width. The electron trapping in the gate insulator via the Fowler-Nordheim tunneling yields the positive voltage shift. As compared to the channel transistor, more trapped electrons at the edge lead to more positive voltage shift and create the hump. The hump is less significant at high temperature due to the thermal excitation of trapped elections via the Frenkel-Poole emission.
Sponsorship	IEEE Electron Devices Society
Starting Page	1332
Ending Page	1335
Page Count	4
File Size	543872
File Format	PDF
ISSN	07413106
Volume Number	29
Issue Number	12
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Thin film transistors MOSFETs Voltage Stress Electron traps Plasma temperature Active matrix liquid crystal displays Plasma displays Silicon compounds Intrusion detection thin-film transistor (TFT) Hump poly-Si positive bias temperature instability (PBTI)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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