NDLI: Performance Fluctuation of FinFETs With Schottky Barrier Source/Drain

Content Provider	IEEE Xplore Digital Library
Author	Zhen Zhang Jun Lu Zhijun Qiu Hellstrom, P.-E. Ostling, M. Shi-Li Zhang
Copyright Year	1980
Abstract	A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.
Sponsorship	IEEE Electron Devices Society
Starting Page	506
Ending Page	508
Page Count	3
File Size	313906
File Format	PDF
ISSN	07413106
Volume Number	29
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fluctuations FinFETs Schottky barriers Electrons Fabrication MOSFETs Silicides Communications technology Laboratories Rapid thermal annealing transmission electron microscopy (TEM) gate underlap platinum silicide PtSi Schottky barrier source/drain (SB-S/D)
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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