NDLI: Improved Electrical Properties of ALD <formula formulatype=inline><tex>$hbox{Hf}_{x} hbox{Zr}_{1 - x}hbox{O}_{2}$</tex></formula> Dielectrics Deposited on Ultrathin PVD Zr Underlayer

Content Provider	IEEE Xplore Digital Library
Author	Triyoso, D.H. Hegde, R.I. Jiang, J. Schaeffer, J.K. Raymond, M.V.
Copyright Year	1980
Abstract	The impact of ultrathin metal underlayer on physical and electrical properties of Hf _x Zr_1- _x O₂(x=~0.4) after high-temperature processing was investigated. An ~5-Aring Zr, ~5-Aring Hf, ~10-Aring Hf metal layer was sputter deposited prior to Hf _x Zr_1- _x O₂ growth. Cross-sectional transmission electron microscopy and secondary ions mass spectrometry analysis confirmed no Zr or Hf silicide formation between the high-k film and Si substrate even after 1000degC processing. No significant increase in equivalent oxide thickness or gate leakage current is observed on devices with metal underlayer. Furthermore, devices with a 5-Aring-thick Zr underlayer exhibited lower threshold voltage, higher mobility, and improved charge trapping characteristics.
Sponsorship	IEEE Electron Devices Society
Starting Page	57
Ending Page	59
Page Count	3
File Size	347906
File Format	PDF
ISSN	07413106
Volume Number	29
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Zirconium Threshold voltage Atherosclerosis High-K gate dielectrics Hafnium oxide Mass spectroscopy Leakage current Silicon Sociotechnical systems MOSFETs tetragonal phase Atomic layer deposition (ALD) charge trapping high- $k$ dielectrics mobility
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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Impacts of Zr Composition in $hbox{Hf}_{1-x} hbox{Zr}_{x}hbox{O}_{y}$ Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics

Factors impacting stabilization of tetragonal phase in Hf high-k dielectrics

Novel Thermally-Stable Hafnium and Zirconium ALD Precursors

Ultrathin HfON Trapping Layer for Charge-Trap Memory Made by Atomic Layer Deposition

Investigation of ALD or PVD (Ti-rich vs. N-rich) TiN metal gate thermal stability on HfO high-K

Reduction of Charge Trapping in $hbox{HfO}_{2}$ Film on Ge Substrates by Atomic Layer Deposition of Various Passivating Interfacial Layers

Comparison of MOCVD- and ALD-Deposited $ hbox{HfZrO}_{4}$ Gate Dielectrics for 32-nm High-Performance Logic SOI CMOS Technologies

Temperature dependant characteristics of scaled NMOS transistors with ultra-thin high-K dielectrics and metal gate electrodes

Demonstration of high performance transistors with PVD metal gate

Improved Electrical Properties of ALD $hbox{Hf}_{x} hbox{Zr}_{1 - x}hbox{O}_{2}$ Dielectrics Deposited on Ultrathin PVD Zr Underlayer

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Impacts of Zr Composition in $hbox{Hf}_{1-x} hbox{Zr}_{x}hbox{O}_{y}$ Gate Dielectrics on Their Crystallization Behavior and Bias-Temperature-Instability Characteristics

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