NDLI: A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices

Content Provider	IEEE Xplore Digital Library
Author	Jeong-Ho Woo Ju-Ho Sohn Hyejung Kim Hoi-Jun Yoo
Copyright Year	1966
Abstract	A 195 mW, 9.1 Mvertices/s fully programmable 3-D graphics processor is designed and implemented for mobile devices. The mobile unified shader provides programmable per-vertex operations and per-pixel operations in a single hardware and thus, it achieves 35% area and 28% power reduction compared with previous architecture. The pixel-vertex multi-threading enhances the 3-D graphics performance by enabling to compute the per-vertex operations and the per-pixel operations at the same time. By adopting the pixel-vertex multi-threading, 94% of the per-vertex operations are interleaved into the per-pixel operations and enhances 3-D graphics performance in real applications. The logarithmic lighting engine and specialized lighting instruction improve the vertex throughput including transform and OpenGL lighting up to 9.1 Mvertices/s, which is 2.5 times higher performance compared with previous works. The proposed 3-D graphics processor is implemented in 3.3 mmtimes3.0 mm using 0.13 mum CMOS process and it was successfully demonstrated on the system evaluation board.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	2370
Ending Page	2380
Page Count	11
File Size	4645087
File Format	PDF
ISSN	00189200
Volume Number	43
Issue Number	11
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Graphics Pipelines Mobile computing Mobile communication Telecommunication computing Digital multimedia broadcasting Information technology Engines Process design Hardware unified shader Low power design programmable 3-D graphics
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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