NDLI: The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Content Provider	IEEE Xplore Digital Library
Author	Nagavarapu, V. Jhaveri, R. Woo, J.C.S.
Copyright Year	1963
Abstract	As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and V_THmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.
Sponsorship	IEEE Electron Devices Society
Starting Page	1013
Ending Page	1019
Page Count	7
File Size	321005
File Format	PDF
ISSN	00189383
Volume Number	55
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Tunneling MOSFET circuits Logic gates Semiconductor process modeling Performance evaluation Junctions Transistors subthreshold swing Band-to-band tunneling $I_{\rm ON}/I_{\rm OFF}$ ratio metal–oxide–semiconductor field-effect transistor (MOSFET) scaling
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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InGaAs/InP Tunnel FETs With a Subthreshold Swing of 93 mV/dec and $I_{rm ON}/I_{rm OFF}$ Ratio Near $hbox{10}^{6}$

Impact of a Spacer–Drain Overlap on the Characteristics of a Silicon Tunnel Field-Effect Transistor Based on Vertical Tunneling

SOI TFET $I_{rm ON}/I_{rm OFF}$ Enhancement via Back Biasing

Impact of a Pocket Doping on the Device Performance of a Schottky Tunneling Field-Effect Transistor

Two-Dimensional Tunnel Transistors Based on ${rm Bi}_{2}{rm Se}_{3}$ Thin Film

DC Compact Model for SOI Tunnel Field-Effect Transistors

Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

${rm Si}_{rm x}{rm Ge}_{1hbox{-}{rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

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