NDLI: BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

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BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

Content Provider	IEEE Xplore Digital Library
Author	Walter, I. Cidon, I. Kolodny, A.
Copyright Year	2002
Abstract	Network-on-chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future chip multi-processor (CMP). However, while NoCs are very efficient for delivering high throughput point-to-point data from sources to destinations, their multi-hop operation is too slow for latency sensitive signals. In addition, current NoCS are inefficient for broadcast operations and centralized control of CMP resources. Consequently, state-of-the-art NoCs may not facilitate the needs of future CMP systems. In this paper, the benefit of adding a low latency, customized shared bus as an internal part of the NoC architecture is explored. BENoC (bus-enhanced network on-chip) possesses two main advantages: First, the bus is inherently capable of performing broadcast transmission in an efficient manner. Second, the bus has lower and more predictable propagation latency. In order to demonstrate the potential benefit of the proposed architecture, an analytical comparison of the power saving in BENoC versus a standard NoC providing similar services is presented. Then, simulation is used to evaluate BENoC in a dynamic non-uniform cache access (DNUCA) multiprocessor system.
Starting Page	61
Ending Page	64
Page Count	4
File Size	141679
File Format	PDF
ISSN	15566056
Volume Number	7
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Network-on-a-chip Delay System-on-a-chip Power system interconnection Broadcasting Scalability Throughput Centralized control Multiprocessing systems Multiprocessor interconnection networks On-chip interconnection networks Interconnection architectures
Content Type	Text
Resource Type	Article
Subject	Hardware and Architecture

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BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP

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BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP