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Development of a New Robot Controller Architecture with FPGA-Based IC Design for Improved High-Speed Performance

Content Provider	IEEE Xplore Digital Library
Author	Xiaoyin Shao Dong Sun
Copyright Year	2005
Abstract	In this paper, a new robot controller architecture is proposed to implement various complex control algorithms for improved high-speed performance. The main thrust of the research is to remove the servo control loop from the digital signal processor (DSP) and implement the high-speed servo loop in a field programmable gate array (FPGA). The main objective of this architecture is to utilize the ultra-high-speed hardwired logic of the FPGA to enhance the overall computational capability and relieve the computational load of the DSP for other tasks. The control algorithm is partitioned into a linear portion and a nonlinear portion. The linear portion with position/velocity feedback represents the major control loop and is implemented in the FPGA. The nonlinear portion acts as dynamic compensation to the linear portion to calculate model-related control gains/parameters, and it is implemented in the DSP. In tandem, with the newly developed control hardware architecture, an FPGA-based motion control integrated circuit (IC) is designed. Experiments are conducted on an industrial robot manipulator to compare the closed-loop performance with this new control architecture and the traditional one, when the same control algorithm is used. The experimental results demonstrate that the proposed new control architecture exhibits much improved motion performance indeed, especially in high-speed motions.
Sponsorship	IEEE Industrial Electronics Society
Starting Page	312
Ending Page	321
Page Count	10
File Size	646792
File Format	PDF
ISSN	15513203
Volume Number	3
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-11-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Robot control High speed integrated circuits Field programmable gate arrays Signal processing algorithms Digital signal processing Motion control Servosystems Digital signal processors Servomechanisms Programmable logic arrays robotic manipulator Field programmable gate array (FPGA) integrated circuit (IC) design motion control
Content Type	Text
Resource Type	Article
Subject	Control and Systems Engineering Information Systems Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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