NDLI: A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

Content Provider	IEEE Xplore Digital Library
Author	Chao You Jong-Ru Guo Kraft, R.P. Chu, M. Goda, B. McDonald, J.F.
Copyright Year	1993
Abstract	A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	1051
Ending Page	1054
Page Count	4
File Size	915011
File Format	PDF
ISSN	10638210
Volume Number	15
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Silicon germanium Germanium silicon alloys Field programmable gate arrays Circuit testing Routing Logic functions Logic testing Sequential analysis Semiconductor device measurement Clocks silicon germanium Current mode logic (CML) field-programmable gate arrays (FPGAs) programmable logic arrays
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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