NDLI: A <emphasis emphasistype=smcaps>mux</emphasis>-based High-Performance Single-Cycle CMOS Comparator

Content Provider	IEEE Xplore Digital Library
Author	Hing-Mo Lam Chi-Ying Tsui
Copyright Year	2004
Abstract	In this brief, a new architecture for high-fan-in CMOS comparator is proposed. The architecture is based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure. By doing so, the fast dynamic MUX significantly improves the overall delay of the high-fan-in comparators. At the same time, a novel high-performance static priority encoder is proposed to generate the control signal for the MUX. A 64-bit MUX-based comparator has been built and compared with the existing fastest single-cycle design in the study by Lam and Tsui (2006). From both the post-layout simulation and test-chip measurement results, it is shown that the performance is improved by around 28%.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	591
Ending Page	595
Page Count	5
File Size	898473
File Format	PDF
ISSN	15497747
Volume Number	54
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks Adders Signal processing algorithms Delay Circuits Digital signal processing Process design Pipeline processing Logic Signal generators parallel-MSB-checking Comparator digital arithmetic high-speed integrated circuits
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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