NDLI: Constraining Transition Propagation for Low-Power Scan Testing Using a Two-Stage Scan Architecture

Content Provider	IEEE Xplore Digital Library
Author	Dong Xiang Li, K. Fujiwara, H. Thulasiraman, K. Jiaguang Sun
Copyright Year	2004
Abstract	A two-stage scan architecture is proposed to constrain transition propagation within a small part of scan flip-flops. Most scan flip-flops are deactivated during test application. The first stage includes multiple scan chains, where each scan chain is driven by a primary input. Each scan flip-flop in the multiple scan chains drives a group of scan flip-flops in the second stage. Scan flip-flops in different stages use separate clock signals. Test signals assigned to scan flip-flops in the multiple scan chains are applied to the scan flip-flops of the second stage in one clock cycle after the test vector has been applied to the multiple scan chains. There exists no transition at the scan flip-flops in the second stage when a test vector is applied to the multiple scan chains
Sponsorship	IEEE Circuits and Systems Society
Starting Page	450
Ending Page	454
Page Count	5
File Size	179536
File Format	PDF
ISSN	15497747
Volume Number	54
Issue Number	5
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-05-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Circuit testing Clocks Energy capture Automatic testing Sun Energy consumption Costs Built-in self-test Combinational circuits test power Clock disabling clock tree test power consumption scan testing test application cost
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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