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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | DiClemente, D. Fei Yuan |
| Copyright Year | 2004 |
| Abstract | This brief introduces current-mode phase-locked loops (PLLs). The proposed current-mode PLLs differ from conventional voltage-mode PLLs by replacing their RC loop filter with a RL loop filter, eliminating the need for large on-chip capacitors. The large inductance of the current-mode loop filter is obtained from CMOS active inductors, taking the advantage of their large and tunable inductance and small silicon area. Both types I and II current-mode PLLs are introduced. Implemented in TSMC 0.18-mum CMOS technology, the simulation results of a 3-GHz current-mode PLL demonstrate that the PLL has the lock time 50 ns, silicon area 2800 mum2, dc power consumption 12.2 mW, and phase noise of -84.5 dBc at 1-MHz frequency offset and the maximum -74 dBc reference spurs |
| Sponsorship | IEEE Circuits and Systems Society |
| Starting Page | 303 |
| Ending Page | 307 |
| Page Count | 5 |
| File Size | 398559 |
| File Format | |
| ISSN | 15497747 |
| Volume Number | 54 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-04-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops Filters Inductance Silicon CMOS technology Voltage Capacitors Active inductors Energy consumption Phase noise current-mode phase-locked loops (PLLs) Current-controlled oscillators (CCOs) current-mode loop filters |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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