NDLI: A Fully Integrated Single-Ended 1.5–15-Hz Low-Pass Filter With Linear Tuning Law

Content Provider	IEEE Xplore Digital Library
Author	Bruschi, P. Nizza, N. Pieri, F. Schipani, M. Cardisciani, D.
Copyright Year	1966
Abstract	A second-order, single-ended, fully integrated low- pass filter with cut-off frequency tunable in the range 1.5-15 Hz is presented. The filter is based on a recently proposed CMOS transconductor topology, combining G_m values of the order of a few nS with large input ranges and suitability to single-ended filter architectures. The circuit has been designed and fabricated using 3.3-V 0.35-mum CMOS devices from the STMicroelectronics Bipolar-CMOS-DMOS process BCD6. The tested prototype occupies an area of 960 x 350 mum² and requires a supply current ranging from 50 to 500 muLambda, depending on tuning. Total harmonic distortion lower than 1% has been measured in a wide tuning range for 1-V peak-to-peak input signal amplitude. The effect of temperature on the tuning law in the interval 0-80degC is shown. A dynamic range in excess of 60 dB over the whole tuning range has been estimated from distortion and noise measurements.
Sponsorship	IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE
Starting Page	1522
Ending Page	1528
Page Count	7
File Size	1070251
File Format	PDF
ISSN	00189200
Volume Number	42
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Low pass filters Nonlinear filters Distortion measurement Tuning Cutoff frequency Tunable circuits and devices Transconductors Circuit topology CMOS process Circuit testing transconductor Analog filter low frequency
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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