NDLI: Testing Analog and Mixed-Signal Circuits With Built-In Hardware

Content Provider	IEEE Xplore Digital Library
Author	Das, S.R. Zakizadeh, J. Biswas, S. Assaf, M.H. Nayak, A.R. Petriu, E.M. Jone, W.-B. Sahinoglu, M.
Copyright Year	1963
Abstract	This paper aims to develop an approach to test analog and mixed-signal embedded-core-based system-on-chips (SOCs) with built-in hardware. In particular, oscillation-based built-in self-test (OBIST) methodology for testing analog components in mixed-signal circuits is implemented in this paper. The proposed OBIST structure is utilized for on-chip generation of oscillatory responses corresponding to the analog-circuit components. A major advantage of the OBIST method is that it does not require stimulus generators or complex response analyzers, which makes it suitable for testing analog circuits in mixed-signal SOC environments. Extensive simulation results on sample analog and mixed-signal benchmark circuits and other circuits described by netlist in HSPICE format are provided to demonstrate the feasibility, usefulness, and relevance of the proposed implementations
Sponsorship	IEEE Instrumentation and Measurement Society Bureau international des poids et mesures IEEE International Bureau of Weights and Measures (BIPM) URSI NBS Agency Ind. Sci. & Technol., Min. Int. Trade & Ind. Sci. Council Japan International Union of Pure and Applied Physics (IUPAP) NIST NRCC National Conference of Standards Laboratories (NCSL) Allen Osborne Associates Andeen-Hagerling, Inc. Ballantine Lab. Inc. Clarke-Hess Communications Research Corp. Fluke Corporation Guildline Instruments Hewlett-Packard Co. Julie Res. Lab. Inc. Keithley Instruments, Inc. Measurements International Ltd. Canada QuadTech Inc. Quantum Design Inc. Rotek Instrum. Corp. Tegam Inc. Tektronix Inc
Starting Page	840
Ending Page	855
Page Count	16
File Size	629033
File Format	PDF
ISSN	00189456
Volume Number	56
Issue Number	3
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Circuit testing System testing Built-in self-test Automatic testing Design engineering System-on-a-chip Integrated circuit testing Manufacturing Information technology Information science test-pattern generator (TPG) Built-in self-test (BIST) circuit under test (CUT) design-for-testability (DFT) mixed-signal test oscillation-based BIST (OBIST) system-on-chip (SOC)
Content Type	Text
Resource Type	Article
Subject	Instrumentation Electrical and Electronic Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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