NDLI: Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme

Content Provider	IEEE Xplore Digital Library
Author	Ohtou, T. Yokoyama, K. Shimizu, K. Nagumo, T. Hiramoto, T.
Copyright Year	1963
Abstract	The bias scheme of the variable body-factor fully depleted (FD) silicon-on-insulator (SOI) MOSFET, which has been previously proposed, is reexamined. Using a new scheme, the inversion and accumulation on the substrate in the active state can be avoided, and thus, ac performance in the active state is not degraded even with extremely thin buried-oxide (BOX), owing to the depletion of the substrate. Moreover, subthreshold leakage can be sufficiently suppressed in the standby state, owing to extremely thin BOX. This scheme provides threshold-voltage adjustability for the suppression of interdie and within-die variation in the active state. This device scheme is also applicable to multichannel FD SOI MOSFETs including FinFETs with a low-aspect-ratio fin, where the back-bias scheme can be applied
Sponsorship	IEEE Electron Devices Society
Starting Page	301
Ending Page	307
Page Count	7
File Size	930634
File Format	PDF
ISSN	00189383
Volume Number	54
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-02-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Back bias, body bias, fully depleted silicon-on-insulator (SOI) MOSFET, interdie variation, thin buried-oxide (BOX), VTCMOS
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control

Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Nanoscale FD/SOI CMOS: thick or thin BOX?

Back-gate mirror doping for fully depleted planar SOI transistors with thin buried oxide

LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme

Similar Documents

Variable-Body-Factor SOI MOSFET With Ultrathin Buried Oxide for Adaptive Threshold Voltage and Leakage Control

Effects of Device Structure and Back Biasing on HCI and NBTI in Silicon-on-Thin-BOX (SOTB) CMOSFET

Analytical Compact Model for Lightly Doped Nanoscale Ultrathin-Body and Box SOI MOSFETs With Back-Gate Control

Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Nanoscale FD/SOI CMOS: thick or thin BOX?

Back-gate mirror doping for fully depleted planar SOI transistors with thin buried oxide

LDD and Back-Gate Engineering for Fully Depleted Planar SOI Transistors with Thin Buried Oxide

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

Threshold-Voltage Control of AC Performance Degradation-Free FD SOI MOSFET With Extremely Thin BOX Using Variable Body-Factor Scheme