NDLI: Multibit Delta-Sigma Modulator With Two-Step Quantization and Segmented DAC

Content Provider	IEEE Xplore Digital Library
Author	Yongjie Cheng Petrie, C. Nordick, B. Comer, D. Comer, D.
Copyright Year	2004
Abstract	An architecture for a multibit single-stage delta-sigma analog-to-digital converter (ADC) with two-step quantization is presented. Both the most significant bit and least significant bit signals produced by the two-step quantization are fed back simultaneously to all integrator stages, making it suitable for low oversampling ratios. The two-step ADC avoids the problem that the complexity of an internal flash ADC increases exponentially with each added bit. A segmented architecture with coarse/fine dynamic element matching (DEM) and digital-to-analog converter (DAC) is proposed to reduce the complexity of DEM and DAC due to the large internal quantizer. The consequence of the segmentation, mismatch between coarse and fine DACs can be noise shaped by using a digital requantization method. Analysis and behavioral simulation results are presented
Sponsorship	IEEE Circuits and Systems Society
Starting Page	848
Ending Page	852
Page Count	5
File Size	295191
File Format	PDF
ISSN	15497747
Volume Number	53
Issue Number	9
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delta modulation Quantization Noise cancellation Circuit noise Clocks Analog-digital conversion Digital-analog conversion Signal to noise ratio Delay Multi-stage noise shaping sigma–delta ( Analog–digital conversion quantization
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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