NDLI: A 16-Bit Barrel-Shifter Implemented in Data-Driven Dynamic Logic (<tex>$D ^3 L$</tex>)

Content Provider	IEEE Xplore Digital Library
Author	Rafati, R. Fakhraie, S.M. Smith, K.C.
Copyright Year	2004
Abstract	Data-driven dynamic logic (D³L) uses local data instead of a global clock to maintain correct precharge and evaluation phases. Eliminating the clock from dynamic gates yields less power consumption and faster gate operation. Two 16-bit barrel shifters are implemented in a 5-V 0.6-mum CMOS technology: one in normal Domino logic and the other in our proposed D³L. Separate power leads are used on the chip to measure power consumption of separate sections. Post-layout simulations show that, depending on input patterns, a D³L shifter consumes 8% to 62% less power and is 29% faster than the Domino circuit. In addition, it provides an additional 9% area advantage over its Domino rival. Experimental measurements confirm post-layout simulation results, and prove the feasibility of the proposed logic
Sponsorship	IEEE Circuits and Systems Society
Starting Page	2194
Ending Page	2202
Page Count	9
File Size	1710405
File Format	PDF
ISSN	15498328
Volume Number	53
Issue Number	10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Clocks CMOS logic circuits Energy consumption Logic design Logic circuits CMOS technology Semiconductor device measurement Circuit simulation Capacitance Power measurement low power design Barrel shifter data-driven dynamic logic ( Domino logic dynamic logic
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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