NDLI: Parallel random number generators for sequences uniformly distributed over any range of integers

Content Provider	IEEE Xplore Digital Library
Author	Kuehnel, R. Yuke Wang
Copyright Year	2004
Abstract	A VLSI design methodology is proposed for the efficient generation of multiple pseudorandom number sequences based on a simplification of Cauwenberghs' counterpropagation technique. We demonstrate that the counterpropagation of two sequences can be replaced by one propagating and one nonpropagating sequence, requiring as few as half the number of flip-flops, while still allowing new circuits to be added to the system without additional calculations-there is no need to keep track of random starting values, tap combinations, or time shifts. Moreover we extend our method from multiple bit sequences to multiple random number sequences that are uniformly distributed over any range of integers. In particular we address the more general problem of generating sequences over the range [0,K] where K+1 is any desired integer, including a power of two or a prime number. To this end we demonstrate that the simple concatenation of random bits to form random bytes is a special case of a more general concept whereby random integers distributed over prime number ranges are concatenated to form random integers distributed over any range. We find that the proposed design compares favorably with design strategies based on cellular automata, both in terms of statistical properties and implementation efficiencies.
Sponsorship	IEEE Circuits and Systems Society
Starting Page	1496
Ending Page	1505
Page Count	10
File Size	672149
File Format	PDF
ISSN	15498328
Volume Number	53
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random number generation Stochastic processes Circuits Computer networks Hardware Artificial neural networks Computer science Very large scale integration Design methodology Flip-flops stochastic logic circuits Cellular automata parallel processing random number generation (RNG)
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Hardware and Architecture

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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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