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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Dengwei Fu Willson, A.N. |
| Copyright Year | 2004 |
| Abstract | An efficient angle-rotation architecture, suitable for use in a digital mixer, is presented. The architecture employs a decomposition of the high-precision rotation-angle into a coarse angle and a fine angle, and employs two processing stages, coarse and fine. Only the coarse stage employs a ROM, and that ROM is extremely small. Small multipliers are shown to suffice while providing full accuracy at the system output. A systematic development of the architecture and its supporting theory and assumptions is given, along with the rationale for determining its structure. A rigorous analysis of its error sources is presented, as well as the computation of bounds for the various errors they induce at the system output. This error analysis is shown to lead to a straightforward means of designing an efficient two-stage angle-rotation unit for a digital mixer, given input/output bitwidths and performance specifications |
| Sponsorship | IEEE Circuits and Systems Society |
| Starting Page | 604 |
| Ending Page | 614 |
| Page Count | 11 |
| File Size | 490307 |
| File Format | |
| ISSN | 15498328 |
| Volume Number | 53 |
| Issue Number | 3 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-03-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Error analysis Read only memory Hardware Delay Computer architecture Synthesizers Frequency Table lookup Arithmetic trigonometric function generation Angle rotation CORDIC direct digital synthesizer (DDS) digital mixer low-latency synchronization |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Hardware and Architecture |
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