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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Misic, J. Shafi, S. Misic, V.B. |
| Copyright Year | 1990 |
| Abstract | The performance of an IEEE 802.15.4 compliant network operating in the beacon enabled mode with both downlink and uplink traffic is analyzed through discrete time Markov chains and the theory of M/G/1 queues. The model considers acknowledged transmissions and includes the impact of different network and traffic parameters such as the packet arrival rate, packet size, inactive period between the beacons, and the number of stations. We investigate the nonsaturation region and outline the conditions under which the network abruptly goes to saturation. The analysis of stability of the network queues shows that the stability of the downlink queue at the coordinator is the most critical for network operation. Due to the abruptness with which the switch from nonsaturation to saturation occurs, the network operating point has to be carefully chosen according to the volume of downlink traffic. Furthermore, our model shows that certain features prescribed by the standard actually limit the performance of 802.15.4 networks. |
| Sponsorship | IEEE Computer Society |
| Starting Page | 361 |
| Ending Page | 376 |
| Page Count | 16 |
| File Size | 2888058 |
| File Format | |
| ISSN | 10459219 |
| Volume Number | 17 |
| Issue Number | 4 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-04-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Downlink Traffic control Telecommunication traffic Queueing analysis Switches Wireless sensor networks Analytical models Stability analysis Network topology Media Access Protocol queuing analysis. IEEE Std 802.15.4 CSMA-CA Medium Access Control (MAC) protocols |
| Content Type | Text |
| Resource Type | Article |
| Subject | Signal Processing Computational Theory and Mathematics Hardware and Architecture |
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