NDLI: Fast interval-valued statistical modeling of interconnect and effective capacitance

Content Provider	IEEE Xplore Digital Library
Author	Ma, J.D. Rutenbar, R.A.
Copyright Year	1982
Abstract	Correlated interval representations of range uncertainty offer an attractive solution to approximating computations on statistical quantities. The key idea is to use finite intervals to approximate the essential mass of a probability density function (pdf) as it moves through numerical operators; the resulting compact interval-valued solution can be easily interpreted as a statistical distribution and efficiently sampled. This paper first describes improved interval-valued algorithms for asymptotic wave evaluation (AWE)/passive reduced-order interconnect macromodeling algorithm (PRIMA) model order reduction for tree-structured interconnect circuits with correlated resistance, inductance, and capacitance (RLC) parameter variations. By moving to a much faster interval-valued linear solver based on path-tracing ideas, and making more optimal tradeoffs between interval- and scalar-valued computations, the delay statistics roughly 10/spl times/ faster than classical Monte Carlo (MC) simulation, with accuracy to within 5% can be extracted. This improved interval analysis strategy is further applied in order to build statistical effective capacitance (C/sub eff/) models for variational interconnect, and show how to extract statistics of C/sub eff/ over 100/spl times/ faster than classical MC simulation, with errors less than 4%.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	710
Ending Page	724
Page Count	15
File Size	874498
File Format	PDF
ISSN	02780070
Volume Number	25
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-04-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitance Integrated circuit interconnections Uncertainty Probability density function Statistical distributions RLC circuits Inductance Delay Statistics Monte Carlo methods statistical analysis Affine arithmetic effective capacitance interconnect modeling
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Interval-Valued Reduced-Order Statistical Interconnect Modeling

Shielding effect of on-chip interconnect inductance

Modeling the Driver Load in the Presence of Process Variations

Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools

Statistical method for the analysis of interconnects delay in submicrometer layouts

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

Modeling the Effective capacitance for the RC interconnect of CMOS gates

Analysis and Modeling of Energy Consumption in RLC Tree Circuits

Equivalent Elmore delay for RLC trees

Fast interval-valued statistical modeling of interconnect and effective capacitance

Similar Documents

Interval-Valued Reduced-Order Statistical Interconnect Modeling

Shielding effect of on-chip interconnect inductance

Modeling the Driver Load in the Presence of Process Variations

Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools

Statistical method for the analysis of interconnects delay in submicrometer layouts

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

Modeling the Effective capacitance for the RC interconnect of CMOS gates

Analysis and Modeling of Energy Consumption in RLC Tree Circuits

Equivalent Elmore delay for RLC trees

Fast interval-valued statistical modeling of interconnect and effective capacitance