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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Srinivasan, R. Cook, J. Lubeck, O. |
| Copyright Year | 2002 |
| Abstract | Cycle accurate simulation has long been the primary tool for micro-architecture design and evaluation. Though accurate, the slow speed often imposes constraints on the extent of design exploration. In this work, we propose a fast, accurate Monte-Carlo based model for predicting processor performance. We apply this technique to predict the CPI of in-order architectures and validate it against the Itanium-2. The Monte Carlo model uses micro-architecture independent application characteristics, and cache, branch predictor statistics to predict CPI with an average error of less than 7%. Since prediction is achieved in a few seconds, the model can be used for fast design space exploration that can efficiently cull the space for cycle-accurate simulations. Besides accurately predicting CPI, the model also breaks down CPI into various components, where each component quantifies the effect of a particular stall condition (branch misprediction, cache miss, etc.) on overall CPI. Such a CPI decomposition can help processor designers quickly identify and resolve critical performance bottlenecks |
| Starting Page | 38 |
| Ending Page | 41 |
| Page Count | 4 |
| File Size | 422493 |
| File Format | |
| ISSN | 15566056 |
| Volume Number | 5 |
| Issue Number | 1 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-01-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Predictive models Monte Carlo methods Computational modeling Sampling methods Computer architecture Laboratories Error analysis Space exploration Process design Mathematical analysis |
| Content Type | Text |
| Resource Type | Article |
| Subject | Hardware and Architecture |
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