NDLI: NANOLAB-a tool for evaluating reliability of defect-tolerant nanoarchitectures

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NANOLAB-a tool for evaluating reliability of defect-tolerant nanoarchitectures

Content Provider	IEEE Xplore Digital Library
Author	Bhaduri, D. Shukla, S.
Copyright Year	2002
Abstract	As manufacturing technology reaches nanoscale, architectural designs need to accommodate the uncertainty inherent at such scales. These uncertainties are germane in the minuscule dimension of the devices, quantum physical effects, reduced noise margins, system energy levels reaching computing thermal limits, manufacturing defects, aging, and many other factors. Defect-tolerant architectures and their reliability measures will gain importance for logic and micro-architecture designs based on nanoscale substrates. Recently, the Markov random field has been proposed as a model of computation for nanoscale logic gates. This opens up new possibilities in designing logic and architecture where the conventional Boolean logic is replaced by a notion of an energy distribution function based on Gibbs distribution. In this computational scheme, probabilities of energy levels at various gate inputs and interconnects are considered, and belief propagation is used to propagate these probability distributions from the primary inputs to the primary outputs of a Boolean network. In this paper, we take this approach further by automating this computational scheme and belief propagation algorithm. We have developed MATLAB-based libraries for fundamental logic gates that can compute probability distributions and entropies at the outputs for specified discrete input distributions and in the presence of noise at the inputs and interconnects. Our tool automates the evaluation of reliability measures of combinational logic blocks. The effectiveness of this automation is illustrated in this paper by automatically deriving various reliability results for defect-tolerant architectures, such as triple modular redundancy (TMR), cascaded TMR, and multistage iterations of these. Also, signal noise is modeled as uniform and Gaussian distributions at the inputs and interconnects, so as to evaluate reliability-redundancy tradeoffs of these architectural configurations taking into account such noise models.
Sponsorship	IEEE Nanotechnology Council
Starting Page	381
Ending Page	394
Page Count	14
File Size	812307
File Format	PDF
ISSN	1536125X
Volume Number	4
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic design Mathematical model Manufacturing Quantum computing Energy states Computer architecture Logic gates Distributed computing Belief propagation Probability distribution triple modular redundancy (TMR) Cascaded triple modular redundancy (CTMR) entropy Gibbs distribution interconnect modeling nanotechnology noise reliability
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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