NDLI: Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Watling, J.R. Lianfeng Yang Asenov, A. Barker, J.R. Roy, S.
Copyright Year	2001
Abstract	Scaling of Si MOSFETs beyond the 90-nm technology node requires performance boosters in order to satisfy the International Technology Roadmap for Semiconductors requirements for drive current in high-performance transistors. Amongst the preferred near term solutions are transport enhanced FETs utilizing strained Si (SSi) channels. Additionally, high-/spl kappa/ dielectrics are expected to replace SiO/sub 2/ around or after the 45-nm node to reduce the gate leakage current problem, facilitating further scaling. However, aside from the many technological issues such as trapped charge and partial crystallization of the dielectric, both of which are major issues limiting the reliability and device performance of devices employing high-/spl kappa/ gate stacks, a fundamental drawback of MOSFETs with high-/spl kappa/ dielectrics is the mobility degradation due to strong soft optical phonon scattering. In this work we study the impact of soft optical phonon scattering on the mobility and device performance of conventional and strained Si n-MOSFETs with high-/spl kappa/ dielectrics using a self-consistent Poisson Ensemble Monte Carlo device simulator, with effective gate lengths of 67 and 25-nm. Additionally we have also briefly investigated the effect (the percentage change) that a trapped charge within the gate oxide will have on the drive current for both a SiO/sub 2/ oxide and an equivalent oxide thickness of high-/spl kappa/ dielectric.
Sponsorship	IEEE Electron Devices Society IEEE Reliability Society
Starting Page	103
Ending Page	108
Page Count	6
File Size	582297
File Format	PDF
ISSN	15304388
Volume Number	5
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-03-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hafnium oxide Optical scattering MOSFETs Dielectric devices Optical devices Phonons FETs Leakage current Charge carrier processes Crystallization soft-optical phonons High- Monte Carlo
Content Type	Text
Resource Type	Article
Subject	Electronic, Optical and Magnetic Materials Safety, Risk, Reliability and Quality Electrical and Electronic Engineering

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Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics

Study of electrically active defects in high mobility HfO/sub 2/ MOSFETs

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

Temperature dependence of channel mobility in HfO/sub 2/-gated NMOSFETs

Modeling of charge trapping induced threshold-voltage instability in high-/spl kappa/ gate dielectric FETs

/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm

Improved thermal stability and device performance of ultra-thin (EOT<10 /spl Aring/) gate dielectric MOSFETs by using hafnium oxynitride (HfO/sub x/N/sub y/)

Carrier transport in HfO/sub 2//metal gate MOSFETs: physical insight into critical parameters

Improvements on surface carrier mobility and electrical stability of MOSFETs using HfTaO gate dielectric

Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs

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Mobility enhancement in strained Si NMOSFETs with HfO/sub 2/ gate dielectrics

Study of electrically active defects in high mobility HfO/sub 2/ MOSFETs

Improvement of surface carrier mobility of HfO/sub 2/ MOSFETs by high-temperature forming gas annealing

Temperature dependence of channel mobility in HfO/sub 2/-gated NMOSFETs

Modeling of charge trapping induced threshold-voltage instability in high-/spl kappa/ gate dielectric FETs

/spl Omega/FETs transistors with TiN metal gate and HfO/sub 2/ down to 10nm

Improved thermal stability and device performance of ultra-thin (EOT<10 /spl Aring/) gate dielectric MOSFETs by using hafnium oxynitride (HfO/sub x/N/sub y/)

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Impact of high-/spl kappa/ dielectric HfO/sub 2/ on the mobility and device performance of sub-100-nm nMOSFETs