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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Staszewski, R.B. Wallberg, J.L. Rezeq, S. Chih-Ming Hung Eliezer, O.E. Vemulapalli, S.K. Fernando, C. Maggio, K. Staszewski, R. Barton, N. Meng-Chang Lee Cruise, P. Entezari, M. Muhammad, K. Leipold, D. |
| Copyright Year | 1966 |
| Abstract | We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power. |
| Sponsorship | IEEE Solid-State Circuits Society IEEE Electron Devices Society IEEE Circuits and Systems Society Japan Society of Applied Physics (JSAP) IEEE Microwave Theory and Techniques Society IEEE San Francisco Section Bay Area Council Univ. PA IEEE |
| Starting Page | 2469 |
| Ending Page | 2482 |
| Page Count | 14 |
| File Size | 1452944 |
| File Format | |
| ISSN | 00189200 |
| Volume Number | 40 |
| Issue Number | 12 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2005-12-01 |
| Publisher Place | U.S.A. |
| Access Restriction | One Nation One Subscription (ONOS) |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Phase locked loops Transmitters Mobile handsets CMOS process MOSFETs Radio frequency Frequency synthesizers Voltage-controlled oscillators GSM Transceivers voltage-controlled oscillators (VCOs) All-digital cellular deep-submicron CMOS digital control digitally controlled oscillator (DCO) frequency synthesizer mobile phones MOS varactor sigma-delta modulator |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering |
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