NDLI: Linearization of the timing analysis and optimization of level-sensitive digital synchronous circuits

Content Provider	IEEE Xplore Digital Library
Author	Taskin, B. Kourtev, I.S.
Copyright Year	1993
Abstract	This paper describes a linear programming (LP) problem formulation applicable to the static-timing analysis of large scale synchronous circuits with level-sensitive latches. Specifically, an LP formulation for the clock period minimization problem is developed. In order to minimize the clock period of level-sensitive circuits, the simultaneous effects of time borrowing and nonzero clock skew scheduling are considered. The clock period minimization problem is formulated for both single-phase and multi-phase clocking schemes. The ISCAS'89 benchmark circuits are used to derive experimental results. LP minimization problems for these benchmark circuits are generated using the modified big M (MBM) method and the generated problems are solved using the industrial LP solver CPLEX . The experimental results demonstrate up to 63% improvements in minimum clock period compared to flip-flop based circuits with zero clock skew.
Sponsorship	IEEE Computer Society Association for Computing Machinery (ACM)/SIGDA IEEE Computer Society Technical Committee on Design Automation
Starting Page	12
Ending Page	27
Page Count	16
File Size	465687
File Format	PDF
ISSN	10638210
Volume Number	12
Issue Number	1
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Circuits Clocks Job shop scheduling Linear programming Minimization methods Latches Flip-flops Iterative methods Large-scale systems
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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