NDLI: Ultrashort SONOS memories

Please wait, while we are loading the content...

Ultrashort SONOS memories

Content Provider	IEEE Xplore Digital Library
Author	Moon Kyung Kim Chae, S.D. Chae, H.S. Kim, J.H. Jeong, Y.S. Jo Won Lee Silva, H. Tiwari, S. Chung Woo Kim
Copyright Year	2002
Abstract	We report the operational characteristics of ultrashort SONOS memories down to /spl sim/30-nm effective gate length. Good sub-threshold swing, good drain-induced barrier lowering (/spl sim/120 mV/decade), and /spl sim/2.4 V of memory window down to the smallest dimensions demonstrate the improvements that result from a thin tunneling oxide and a large trapping center density. The use of distributed defects and thin tunneling oxide is reflected in a memory window that is stable up to at least 10/sup 5/ cycles for the smallest devices. The smallest structures tested employ /spl sim/75 electrons for memory storage, which allows for device to device reproducibility. The capture and emission processes asymmetries point to the differences in the energy parameters of the two processes. The smallest structures, however, do show loss of retention time compared to the larger structures, for the same oxide-nitride-oxide stack thickness, and this is believed to arise from higher leakage due to higher defects distribution in the gate insulators from process-induced damage. All tested devices, down to /spl sim/30-nm effective gate length, show very good endurance characteristics.
Sponsorship	IEEE Nanotechnology Council
Starting Page	417
Ending Page	424
Page Count	8
File Size	480500
File Format	PDF
ISSN	1536125X
Volume Number	3
Issue Number	4
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	SONOS devices Silicon on insulator technology Nanocrystals Tunneling Electron traps Testing Reproducibility of results Insulation Nonvolatile memory Voltage silicon–oxide–nitride–oxide–silicon (SONOS) memory CMOS device scaling nonvolatile memory scaling limits silicon-on-insulator (SOI) technology
Content Type	Text
Resource Type	Article
Subject	Nanoscience and Nanotechnology Electrical and Electronic Engineering Computer Science Applications

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Polarity-dependent device degradation in SONOS transistors due to gate conduction under nonvolatile memory operations

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

Three-dimensional Simulation of the dependence of the programming window of SOI nanocrystal memories on the channel width

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

Optimisation and Simulation of an Alternative nano-flash Memory: the SASEM device

Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

Ultrashort SONOS memories

Similar Documents

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Polarity-dependent device degradation in SONOS transistors due to gate conduction under nonvolatile memory operations

Si-Nanowire Based Gate-All-Around Nonvolatile SONOS Memory Cell

Three-dimensional Simulation of the dependence of the programming window of SOI nanocrystal memories on the channel width

Process Optimization and Downscaling of a Single-Electron Single Dot Memory

SONOS-type flash memory using an HfO/sub 2/ as a charge trapping layer deposited by the sol-gel spin-coating method

Performance and reliability features of advanced nonvolatile memories based on discrete traps (silicon nanocrystals, SONOS)

Optimisation and Simulation of an Alternative nano-flash Memory: the SASEM device

Suppression of erased state V/sub t/ drift in two-bit per cell SONOS memories

Ultrashort SONOS memories