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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Adir, A. Almog, E. Fournier, L. Marcus, E. Rimon, M. Vinov, M. Ziv, A. |
| Copyright Year | 1984 |
| Abstract | Functional verification is widely recognized as the bottleneck of the hardware design cycle. With the ever-growing demand for greater performance and faster time to market, coupled with the exponential growth in hardware size, verification has become increasingly difficult. Although formal methods such as model checking and theorem proving have resulted in noticeable progress, these approaches apply only to the verification of relatively small design blocks or to very focused verification goals. Current industry practice is to use separate, automatic, random stimuli generators for processor- and multiprocessor-level verification. The generated stimuli, usually in the form of test programs, trigger architecture and microarchitecture events defined by a verification plan. MAC-based algorithms are well suited for the test program generation domain because they postpone heuristic decisions until after consideration of all architectural and testing-knowledge constraints. Geneysys-Pro is currently the main test generation tool for functional verification of IBM processors, including several complex processors. We've found that the new language considerably reduces the effort needed to define and maintain knowledge specific to an implementation and verification plan. |
| Sponsorship | IEEE Computer Society |
| Starting Page | 84 |
| Ending Page | 93 |
| Page Count | 10 |
| File Size | 366594 |
| File Format | |
| ISSN | 07407475 |
| Volume Number | 21 |
| Issue Number | 2 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) Computer Society |
| Publisher Date | 2004-03-01 |
| Publisher Place | U.S.A. |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Technological innovation Testing Engines Design engineering Knowledge engineering Microprocessors Computer languages Power generation Spine Power system modeling |
| Content Type | Text |
| Resource Type | Article |
| Subject | Electrical and Electronic Engineering Software Hardware and Architecture |
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