NDLI: Software detection mechanisms providing full coverage against single bit-flip faults

Content Provider	IEEE Xplore Digital Library
Author	Nicolescu, B. Savaria, Y. Velazco, R.
Copyright Year	1963
Abstract	Increasing design complexity for current and future generations of microelectronic technologies leads to an increased sensitivity to transient bit-flip errors. These errors can cause unpredictable behaviors and corrupt data integrity and system availability. This work proposes new solutions to detect all classes of faults, including those that escape conventional software detection mechanisms, allowing full protection against transient bit-flip errors. The proposed solutions, particularly well suited for low-cost safety-critical microprocessor-based applications, have been validated through exhaustive fault injection experiments performed on a set of real and synthetic benchmark programs. The fault model taken into consideration was single bit-flip errors corrupting memory cells accessible to the user by means of the processor instruction set. The obtained results demonstrate the effectiveness of the proposed solutions.
Sponsorship	IEEE Nuclear and Plasma Sciences Society Computer Applications in Nuclear and Plasma Sciences (CANPS) Lawrence Berkeley Lab. Lawrence Livermore Nat. Lab. APS College of William and Mary Continuous Electron Beam Accelerator Facility NASA Defence Nuclear Agency Sandia National Laboratories Jet Propulsion Laboratory Brookhaven Nat. Lab. Lawrence Livermore Nat. Lab IEEE/NPPS Radiat. Effects Committee Defence Nuclear Agency/DoD Sandia National Laboratories/DOE Jet Propulsion Laboratory/NASA Phillips Lab./DoD
Starting Page	3510
Ending Page	3518
Page Count	9
File Size	623689
File Format	PDF
ISSN	00189499
Volume Number	51
Issue Number	6
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-12-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fault detection Circuit faults Application software Hardware Redundancy Microelectronics Monitoring Electrical fault detection Very large scale integration Error correction software error detection Control flow checking data computing block (DCB) exhaustive fault injection experiments signature monitoring technique
Content Type	Text
Resource Type	Article
Subject	Nuclear and High Energy Physics Electrical and Electronic Engineering Nuclear Energy and Engineering

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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