NDLI: Layout driven retiming using the coupled edge timing model

Content Provider	IEEE Xplore Digital Library
Author	Neumann, I. Kunz, W.
Copyright Year	1982
Abstract	Retiming is a widely investigated technique for performance optimization. It performs powerful modifications on a circuit netlist. However, often it is not clear whether the predicted performance improvement is still valid after placement has been performed. This paper presents a new retiming algorithm using a highly accurate timing model. It takes into account the effect of retiming on capacitive loads of single wires as well as fanout systems. Further, we propose the integration of retiming into a timing-driven standard cell placement environment. Retiming is used as an optimization technique throughout the whole placement process. The experimental results show the benefit of the proposed approach. In comparison with the conventional design flow based on the standard FEAS algorithm, our approach achieved an improvement in cycle time of up to 34% and 17% on the average.
Sponsorship	IEEE Council on Electronic Design Automation IEEE Circuits and Systems Society
Starting Page	825
Ending Page	835
Page Count	11
File Size	978951
File Format	PDF
ISSN	02780070
Volume Number	22
Issue Number	7
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-07-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Timing Registers Delay Semiconductor device modeling Coupling circuits Optimization Logic testing Circuit testing CMOS technology Power system modeling
Content Type	Text
Resource Type	Article
Subject	Computer Graphics and Computer-Aided Design Electrical and Electronic Engineering Software

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Placement driven retiming with a coupled edge timing model

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